`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/11/08 08:38:05
// Design Name: 
// Module Name: fpga_top_3class
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

`include "counter_def_class3.vh"

module fpga_top_3class(
    input  wire clk,
    input  wire BTN0,
    input  wire BTN1,
    input  wire BTN2,
    input  wire BTN3,
    input  wire SW0,
    input  wire SW1,
    output wire led0,
    output wire led1,
    output wire led2,
    output wire led3 
    );
 
    
    
 //BTN0:复位
 //BTN1：c_stop
 //led0：pwm
 //SW0 :c_dir[0]
 //SW1 :c_dir[1]
 
 reg [1:0] c_dir;
 reg [`CNT_WIDTH-1:0] c_crr;
 
 key_debounce_3class u_key_debounce_BTN0(.clk    (clk),.BTNx   (BTN0),.BTNx_D (BTN0_D)); 
 key_debounce_3class u_key_debounce_BTN1(.clk    (clk),.BTNx   (BTN1),.BTNx_D (BTN1_D)); 
 key_debounce_3class u_key_debounce_BTN2(.clk    (clk),.BTNx   (BTN2),.BTNx_D (BTN2_D)); 
 key_debounce_3class u_key_debounce_BTN3(.clk    (clk),.BTNx   (BTN3),.BTNx_D (BTN3_D));
 //换名字
assign  rst   = BTN0_D;
assign  c_rst = BTN1_D;
always @(posedge clk or negedge rst)begin
    if(!rst)begin
         c_dir <=2'b1;
    end
    else if(SW0==0 && SW1 == 0)begin
         c_dir <=2'b0;
    end
    else if(SW0==1 && SW1 == 0)begin
         c_dir <=2'b1;
    end
    else if(SW0==0 && SW1 == 1)begin
         c_dir <=2'h2;
    end
    else ;
end    

always @(posedge clk or negedge rst)begin
    if(!rst)begin
        c_crr <= {`CNT_WIDTH{1'b1}}>>1;
    end
    else begin
        c_crr <= {`CNT_WIDTH{1'b1}}>>1;
    end
end    

assign led = pwm;

counter_top_2class counter_top_2class(
    .clk        (clk),
    .rst        (rst),
    .c_rst      (c_rst),
    .c_stop     (c_stop),
    .c_dir      (c_dir), //1向上，0向下
    .c_crr      (c_crr),
    .pwm        (pwm)
 );
 
endmodule
